1. Field of the Invention
The present invention generally relates to semiconductor memory devices, and particularly relates to a semiconductor memory device such as a DRAM which stores data in a cell array thereof.
2. Description of the Related Art
In semiconductor memory devices such as DRAMs, memory cells, each of which is capable of storing 1 bit of data, are grouped into a plurality of blocks, and data is written in or read from a memory cell array of each of these blocks. FIG. 1 is an illustrative drawing showing a layout of cell arrays and peripherals thereof with regard to a related-art DRAM.
A DRAM of FIG. 1 includes a core circuit 201 and global data buses 202 for reading data from and writing data in the core circuit 201. The core circuit 201 includes cell blocks 210, sense-amplifier-line areas 211, sub-word-decoder-line areas 212, local data buses 213, a word-selection line 214, a column-selection line 215, and amplifier switches 216. The cell blocks 210 are arranged in rows and columns, and include cell arrays. The sense-amplifier-line areas 211 are provided alongside the cell blocks 210 on either one of an upper side and a lower side thereof. The sub-word-decoder-line areas 212 are positioned alongside the cell blocks 210 on either one of a left-hand side and a right-hand side. The local data buses 213 are laid out over the sense-amplifier-line areas 211. The word-selection line 214 selects a row of memory cells in the cell blocks 210. The column-selection line 215 selects some of sense amplifiers (not shown) which are arranged in the sense-amplifier-line areas 211. The amplifier switches 216 connects the local data buses 213 to the global data buses 202.
Operations of the DRAM of FIG. 1 will be described below by taking a data-read operation as an example. The word-selection line 214 is first selected from a plurality of word-selection lines (not shown) by word decoders (not shown) arranged in the sub-word-decoder-line areas 212. The selection of the word-selection line 214 is equivalent to selecting one row of the cell blocks 210 from the rows and columns of the cell blocks 210, and further selecting a row of memory cells from the cell arrays in the selected row of the cell blocks 210. Data stored in the selected memory cells is transferred via bit lines (not shown) to the sense amplifiers provided in the sense-amplifier-line areas 211 which are arranged on the upper side and the lower side of the selected cell blocks 210. The column-selection line 215 is selected from a plurality of column-selection lines (not shown) to choose some sense amplifiers from the plurality of sense amplifiers, which store the data transferred from the memory cells. The data is read from the selected sense amplifiers to the local data buses 213. The amplifier switches 216 are operated to connect the global data buses 202 to the local data buses 213 which are situated on the upper side and the lower side of the selected cell blocks 210. This allows the global data buses 202 to read data from the local data buses 213.
In the related-art DRAM having such a layout as described above, spaces need to be provided on either side of the core circuit 201 to accommodate the global data buses 202. Providing such spaces entails an increase in a chip size, and, thus, is not desirable. Further, the amplifier switches 216 for connecting between the global data buses 202 and the local data buses 213 are bound to have some resistance. The problem is that this resistance slows data-transfer speed.
FIG. 2 is an illustrative drawing showing another layout of cell arrays and peripherals thereof with regard to a related-art DRAM.
In FIG. 2, the same elements as those of FIG. 1 are referred to by the same numerals, and a description thereof will be omitted. In a DRAM of FIG. 2, global data buses 202A are positioned on either side of each columns of the cell blocks 210, which are arranged in rows and columns inside a core circuit 201A. The local data buses 213 are connected to the global data buses 202A via amplifier switches 216A, which are provided at intersections between the local data buses 213 and the global data buses 202A.
In the layout of FIG. 2, the global data buses 202A are overlaid on the sub-word-decoder-line areas 212, so that there is no need to provide spaces dedicated for the global data buses as shown in FIG. 1. The layout, however, is relatively complex in that the global data buses 202A, the amplifier switches 216A, and circuits (not shown) for driving the amplifier switches 216A need to be arranged over the sub-word-decoder-line areas 212.
Further, there is a serious problem which are shared by both the layout of FIG. 1 and the layout of FIG. 2. The problem is that since the global data buses 202 or 202A are laid out within a limited small space, a limitation is placed on the number of the global data buses which can be laid out. Namely, there is a size limit to available chip areas, so that it is difficult to step up the volume of data transfer by increasing the number of global data buses.
Accordingly, there is a need for a semiconductor memory device which can step up the volume of data transfer by increasing the number of global data buses without enlarging a chip size.